1. Field of the Invention
The invention relates to a memory circuit and, more particularly, a non-volatile static semiconductor memory circuit.
2. Description of the Prior Art
A non-volatile read-write random access memory as one of the conventional non-volatile semiconductor memory circuits is discussed in a paper "A 256 Bit Non-volatile Static Random Access Memory with MNOS Memory Transistors" by S. Saito, N. Endo, Y. Uchida, T. Tanaka, Y. Nishi and K. Tamaru, Proceedings of the 7th Conference on Solid State Devices, Tokyo, 1975, pp. 185-190. The memory in the paper employs non-volatile memory cells as shown in FIG. 1. In the figure, transistors T1 T2, T7 and T8 are P-channel enhancement type MOS transistors; transistors T3 and T4, P-channel depletion type MOS transistors; transistorsMT1 and MT2, metal nitride oxide semiconductor (MNOS) transistors of the P-channel variable threshold type.
In the MNOS transistor, the gate insulating layer is formed by double layers; a nitride layer (Si3N4) and a very thin oxide layer (SiO2). The charge transfer is made between a trap level existing in the vicinity of the interface between the nitride and oxide layers, and the substrate, through the tunnel phenomena in the extremely thin oxide layer, and the levels of the gate threshold voltage of the transistor are made to correspond to the binary information "1" and "0". The information are stored in a non-volatile manner.
The transistors T7 and T8 serve each as a switching transistor. When these transistors are turned on, the circuit operates as a single-channel, MOS type circuit at the time that a power source is in a stable state. When the power source is in a transient state, information transfer is performed between the single-channel, MOS type circuit and the MNOS transistors MT1 and MT2. In this way, the above-mentioned circuit serves as a memory cell of the non-volatile read write random access memory type.
The memory circuit, however, has mainly the following two grave defects. One is a large power consumption of each memory. In the memory cell of the single channel type, DC current flows into at least one of the load transistors T3 and T4 in a stable operation mode. Further, in order to prohibit the write-operation into the MNOS transistor, the power source voltage .vertline.V.sub.DD -V.sub.SS .vertline. (where V.sub.DD is a power source voltage and V.sub.SS is a ground voltage) must be large. For this, the power consumption per memory cell takes a great value in the order of several hundreds microwatt. Another defect is that a large value, for example, -20 V, is necessary for the power source voltage (V.sub.DD -V.sub.SS).
The necessity of such a large power source voltage is undesirable when the integration density the reliability, and the like are taken into consideration. In the light of this, the development of the memory circuit operable by a lower power source has long been desired.